Ruben Purdy

ruben (dot) purdy (at) gmail (dot) com

rpurdy (at) andrew (dot) cmu (dot) edu

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I'm a Ph.D. student in the department of Electrical and Computer Engineering at Carnegie Mellon University, where I am grateful to be advised by Dr. Shawn Blanton.

headshot

Broadly, my research interests are in integrated circuit test, hardware security, and energy-efficient machine learning. Recently, I've been focusing on a novel physical-region based logic circuit test and diagnosis methodology. During my time at CMU I have been awarded various fellowships and interned at Apple on the Design for Test team. I got my B.S. in Electrical and Computer Engineering at the University of Arizona where I worked on architectures and algorithms for neuromorphic computing in Dr. Akoglu's Reconfigurable Computing Lab. Before that I did iOS development for the University of Arizona.

I also helped build CircuitGraph, a library for working with hardware designs as graphs.

My full CV is available here.

Publications

R. Purdy, C. Nigh, W. Li and R.D. Blanton, “CHEF: CHaracterizing Elusive Logic Circuit Failures,” VLSI Test Symposium. IEEE, 2025. [To Appear]
C. Nigh, R. Purdy, W. Li, S. Mitra and R.D. Blanton, “Faulty Function Extraction for Defective Circuits,” European Test Symposium. IEEE, 2024.
Wei Li, Ruben Purdy, Jose Moura, Shawn Blanton, “Characterize the ability of GNNs in attacking logic locking”, Workshop on Machine Learning for CAD. ACM/IEEE, 2023.
Y. Qin, R. Purdy, A. Probst, C. Lin, and J. Zhu. “Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS,” Journal of Solid-State Circuits. IEEE, 2023.
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Y. Qin, R. Purdy, A. Probst, C. Lin, and J. Zhu. “ASIC Implementation of Non-linear CNN-based Data Detector for TDMR System in 28nm CMOS at 200Mbits/s Throughput,” Transactions on Magnetics. IEEE, 2022.
Y. Qin, R. Purdy, A. Probst, C. Lin, and J. Zhu. “Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS,” Symposium on VLSI Circuits. IEEE, 2022.
R. Purdy and R.D. Blanton. “Large-Scale Logic-Locking Attacks via Simulation,” International Symposium on Quality Electronic Design. IEEE, 2022.
Mack, Joshua, et al. "RANC: Reconfigurable Architecture for Neuromorphic Computing." Transactions on Computer-Aided Design of Integrated Circuits and Systems. IEEE, 2020.
S. Valancius, et al. “FPGA Based Emulation Environment for Neuromorphic Architectures,” International Parallel and Distributed Processing Symposium Workshops. IEEE, 2020.

Awards

'24
Qualcomm Innovation Fellowship
'24
Apple PhD Fellowship in Integrated Systems
'21
David H. Barakat and LaVerne Owen-Barakat Dean's Fellowship